1. Field of the Invention
This invention generally relates to methods for identifying array areas in dies formed on a wafer and methods for setting up such methods. Certain embodiments relate to identifying array areas in dies formed on a wafer based on areas in a search area image acquired for the wafer that are determined to substantially match an array pattern in a template image or one or more attributes of texture in a training image.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a specimen such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that typically involves transferring a pattern to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.
Wafer inspection using either optical or electron beam imaging are important techniques for debugging semiconductor manufacturing processes, monitoring process variations, and improving production yield in the semiconductor industry. With the ever decreasing scale of modern integrated circuits (ICs) as well as the increasing complexity of the manufacturing process, inspection becomes more and more difficult.
In each processing step performed on a semiconductor wafer, the same circuit pattern is printed in each die on the wafer. Most wafer inspection systems take advantage of this fact and use a relatively simple die-to-die comparison to detect defects on the wafer. However, the printed circuit in each die may include many areas of patterned features that repeat in the x or y direction such as the areas of DRAM, SRAM, or FLASH. This type of area is commonly referred to as an array area (the rest of the areas are called random or logic areas). To achieve better sensitivity, advanced inspection systems employ different strategies for inspecting the array areas and the random or logic areas.
Examples of inspection systems configured for array area inspection are described in commonly assigned U.S. Pat. No. 4,845,558 to Tsai et al., which is incorporated by reference as if fully set forth herein. In the systems described by Tsai et al., generally, the system adjusts the zoom of an image sensor such that each cell of an array pattern in the array area fits exactly into some integer number of pixels. The system then performs a cell-to-cell comparison by simply shifting the image sensor one cell away on the wafer and acquiring an image at the shifted location. This array inspection strategy can achieve much higher sensitivity in array areas than random inspection because it avoids noise caused by die-to-die variation and the residue error of image interpolation when registering one die image to another die image that have different image sizes.
To set up a wafer inspection process for array inspection, many currently used inspection systems require users to manually define the array areas of a die. This step is commonly referred to as care area setup, where the care areas (or the areas that the user cares about) are the array areas. Since modern chip design is getting more and more complex, the number of care areas and the complexity of their layout continues to increase. As a result, users may have to spend hours in defining the array care areas. Some users, due to the lack of time, simply skip the array care area setup and inspect the array area in random mode, thus losing the sensitivity entitlement provided by the inspection system.
Furthermore, in the manual method, the user may have to setup thousands of care areas for array region/geometry manually. Even with some user interface (UI) helper functions for copying and filling care areas, manual care area setup is still a tedious and error-prone process. For example, there is always a possibility that the user will draw the care areas inaccurately and/or mistakenly include page breaks in the care areas. Care area inaccuracy can reduce the care areas included in the inspected area by missing some care areas during the inspection, and missing page breaks results in “blowups” during the inspection. In order to fix the blowup problem, the user has to redefine the care areas or remove the page breaks from the care areas thereby further increasing the overall recipe setup time quite significantly.
Examples of methods for attempting to automate the care area setup are described in U.S. Pat. No. 7,065,239 to Maayah et al., which is incorporated by reference as if fully set forth herein. In the methods described in this patent, generally, the array areas are detected as part of a defect detection algorithm. To find array areas in an image, the image is divided into relatively small blocks and an array-metric is determined for each block. The array-metric represents the likelihood that the block includes an array pattern. The method then applies a pre-defined threshold to the metric to classify each block as an array or random block. Finally, the method merges connected array blocks into array areas.
There are, however, several drawbacks to the methods described in this patent. For example, the array-metric used in these methods may not be a strong discriminator for some array patterns. Therefore, the classification of array blocks may be relatively inaccurate thereby resulting in error in the identification of the array areas. In addition, the spatial resolution of the identified array areas is limited by the size of the blocks. Furthermore, the array area finding is performed during run-time. Therefore, if there are any errors in the array area identification, users will not have the chance to verify and correct the errors. In addition, since this array area finding is performed at run time instead of during setup, these methods increase the time required to run wafer inspections thereby reducing the throughput (e.g., number of wafers inspected per hour) of the inspection system.
Accordingly, it would be advantageous to develop methods for identifying array areas in dies formed on a wafer and methods for setting up such methods, which can be used to automatically identify array areas in the dies on the wafer, and which can reduce care area setup time from hours to minutes thereby greatly improving the ease of use of inspection systems and achieving the maximum sensitivity entitlement for inspection of array areas provided by the inspection systems.